Synthesizing Vectorizing Compilers with EGraphs and Rule Synthesis
2024-09-19
Samuel will present his ASPLOS 2024 work, Automatic Generation of Vectorizing Compilers for Customizable Digital Signal Processors.
Abstract
In this talk, I will present my work on Isaria: a technique to use equality saturation and rule synthesis to automatically synthesize vectorizing compilers for DSP architectures. Isaria takes in a specification of the instruction set for a target DSP and can synthesize a set of rewrite rules that we can use to construct a compiler. Isaria automatically discovers phase structure in the rules, that it uses to schedule rule application in the EGraph to make equality saturation tractable. Isaria can generate compilers that can out-perform hand-written expert compilers.
Speaker
Samuel Thomas (he/him) is a 4th year PhD student currently studying at UT Austin under James Bornholt. He’s interested in making domain specific hardware more accessible to programmers using programming language design and program synthesis techniques. He was worked on the Calyx compiler infrastructure, which is a toolchain to compile languages down to hardware. He has also won the Best Paper award for his work at ASPLOS ‘24 on automatically synthesizing compilers using equality saturation and rule synthesis.